1. Field of the Invention
Various embodiments relate to a semiconductor device, and more particularly, to a technology for shortening a test time of a semiconductor device.
2. Description of the Related Art
As semiconductor-related technologies are developed, the operation speed of a semiconductor memory device is gradually increasing. Among semiconductor devices, an SDRAM (synchronous dynamic random access memory) operates in synchronization with an external clock. Recently, a DDR (double data rate) type SDRAM has been used, in which data is inputted and outputted in synchronization with a clock not only at the rising edge of the clock but also at the falling edge of the clock, thereby increasing a data transmission rate. In a DDR SDRAM, DDR2 and DDR3 types have been developed and used following a DDR1 type. In the case of the DDR1 type, 2-bit prefetch is performed and the burst length (BL) of input/output data becomes 2. In the case of the DDR2, 4-bit prefetch is performed and the burst length becomes 4. In the case of the DDR3, 8-bit prefetch is performed and the burst length becomes 8. The burst length of 8 means that 8-bit data synchronized with a clock is consecutively inputted and outputted through one data input/output pad.
In the case where a memory device is applied with a read command and performs a read operation for outputting stored data, a certain time is required for the data stored in a memory cell region to be outputted to an outside of the memory device through an internal circuit. Accordingly, the read command applied from the outside should have a minimum time interval, that is, a column address strobe (CAS) to column address strobe (CAS) delay time (tCCD). For example, when a DDR3 SDRAM performs a read operation with the burst length of 8, a time interval between consecutively applied read commands should be 4tCK at the minimum.
Meanwhile, in order to improve the slope of a global input/output signal, a semiconductor memory device has a read global bus and a write global bus instead of one global bus. The write global bus transfers data from data pads to a cell array when writing data. The read global bus transfers data from a cell array to data pads when reading data.
As a semiconductor memory device is highly integrated with the development of processing technologies, in order to ensure the reliability of a chip, a test is performed through a long time using expensive test equipment after fabrication. In order for such a test of a memory device, efforts have been made to shorten and reduce a time and a cost required for performing the test, by embedding in advance a self-test circuit in a chip during a design stage.
When using test equipment for verifying the product characteristics and functions of a semiconductor chip, in order to reduce a cost, as large a number of semiconductor chips as possible should be tested through one test. Further, in order to test a large number of semiconductor chips through channels which are allocated to each equipment, entire memory chips should be tested using as small a number of input/output lines as possible.
In parallel test equipment, in order to shorten a test time, a self-test mode called a DQ (data) compression test is used. Such a data compression test as a kind of a self-test is a method in which the same data are stored in a plurality of memory cells, the stored data are simultaneously outputted, the simultaneously outputted data are compressed, and results are compared, to test the occurrence of an error in a memory.
In the case of performing the data compression test, since compressed data are outputted, the number of data output channels (that is, data pads) to be used may be minimized. Therefore, the data compression test may allow a number of dies to be simultaneously tested.
For example, a semiconductor chip undergoes various tests to be verified in the characteristics and functions of a product. In order to reduce a cost when using equipment for testing a semiconductor chip, it is necessary to test as large a number of semiconductor chips as possible through one test.
In order to test a large number of semiconductor chips, entire chips should be tested using as small a number of input/output (GIO) lines as possible. As one of such methods, a multi-bit parallel test method has been widely known in the art.
Such a multi-bit parallel test method has an advantage in that, since a pass or a fail is determined by simultaneously writing data in a plurality of cells and comparing the output values of the plurality of cells, a test time may be significantly shortened. In order to test as large a number of chips as possible by using channels allocated to each test equipment, the number of input/output lines of a semiconductor memory to be used in a test is being decreased.
If a fail occurs in one chip during a packaging stage after the multi-bit parallel test of a wafer and a product, such as an MCP (multi-chip package), a DDP (double die package) and a QDP (quad die package), which is fabricated by stacking a number of chips, is resultantly failed, losses in terms of economy and time cannot help but be substantial.